One of the primary advantages of Gen-Z technology is its ease of integration with multiple solution types, including clients, servers, storage, embedded and message-based communications. Our latest white paper outlines how Gen-Z and RISC-V can be combined in integrated processor designs.
RISC-V was created to be an open, free Instruction Set Architecture (ISA), intended to unlock processor innovation and increase processor solution and industry agility.
Bringing these two new, innovative technologies together just makes sense. RISC-V’s large address space, secured privileged execution environment, and extensible ISA naturally aligns with Gen-Z’s scalability, built-in security and hardware-enforced isolation, and robust and easily extensible functionality.
In addition, there are multiple processor and accelerator innovation opportunities using Gen-Z, which include:
- Gen-Z Memory Management Unit (ZMMU) to transparently support memory at any scale;
- PCIe® Enhanced Configuration Access Method (PECAM) and Logical PCIe Devices (LPD) to enable massive scale-out storage solutions;
- Atomics to simplify multi-component coordination, buffer operations, and pattern/regular expression offload;
- DRAM emergency back-up services;
- DMTF Redfish hardware and security management;
- Ethernet and HPC messaging over Gen-Z