Below you will find a collection of frequently asked questions and answers. If you have additional questions or would like to meet with a Consortium representative, please Contact Us.
Gen-Z is an open systems fabric-based architecture designed to provide high-speed, low-latency, secure access to data and devices. Learn more by viewing our video — An Introduction to Gen-Z Technology.
Yes, Gen-Z is developed by the Gen-Z Consortium, an open industry consortium incorporated and formally formed on August 18, 2016. See a current list of Gen-Z specifications as well as a current list of Members.
Gen-Z was developed to enhance existing solution architectures and enable new solution architectures, while increasing performance (high-bandwidth, low-latency), software efficiency, power optimization, security, and industry agility.
- MEMORY MEDIA INDEPENDENCE. Gen-Z abstracts the memory media to enable any type and mix of DRAM and non-volatile memory (NVM) to be directly accessed by applications or through block-semantic communications.
- HIGH-BANDWIDTH, LOW LATENCY. Gen-Z provides an efficient, memory-semantic protocol that simplifies hardware and software designs, reducing solution cost and complexity by supporting a wide range of signaling rates and link widths that enable solutions to scale from tens to several hundred GB/s of bandwidth with sub-100ns load-to-use memory latency.
- MULTIPATH. Increases aggregate component performance and enables very high signaling rates, solution resilience to prevent loss of data access, and traffic segregation to allow services and applications to be isolated from one another.
- SCALABILITY. Scales from simple point-to-point optimized solutions to rack-scale, switch-based topologies without sacrificing performance or solution flexibility.
- SECURITY & ISOLATION. Supports a combination of hardware-enforced isolation techniques. More information here.
- ADVANCED WORKLOADS & TECHNOLOGIES. Supports hybrid and data-centric computing to deliver high-performance and power-optimized solutions.
- MECHANICAL COMPATIBILITY. Can be incorporated into any solution using a wide range of existing mechanical form factors and cables, enabling Gen-Z to be integrated into existing platforms and solution stacks. More information here.
- SOFTWARE COMPATIBILITY. Supports unmodified operating systems, unmodified applications, and middleware and unmodified I/O device drivers to enable Gen-Z to be integrated into existing solutions.
- HIGH-SPEED SIGNALING RATES. Gen-Z has the immediate capability of 56 GT/s with a path to 112 GT/s and beyond.
- HIGH-EFFICIENCY PROTOCOL. High protocol efficiency provides greater performance and reduces the power required to deliver a given bandwidth.
All final and draft Gen-Z specifications are currently available to the public and can be downloaded via our specifications page.
Gen-Z specifies a packet protocol. The protocol packets are transported across serial links that connect components. The Gen-Z protocol uses memory-semantic communications to move data between the components.
Memory-semantic communications are used to move data between memories located on different components with minimal overhead. Learn more here.
Memory-semantic communications minimize protocol overhead and transaction latency. The efficiency and simplicity of memory-semantic communications are critical to delivering optimal performance and power consumption, which directly impact customer capital (CapEx) and operational (OpEx) costs.
By centralizing resources such as memory, GPU and SCM, Gen-Z eliminates underutilized, stranded memory capacity. Removing collocated resources saves in power, component replacement downtime, and resource reuse, reducing system costs of ownership.
To access data, the component and associated address ranges are advertised to the communicating components. Once advertised and mapped and/or configured into each communicating component’s address space, the components use memory-semantic communications to directly access each other’s data. Components use low-latency read and write operations to directly access up to 256 bytes of data request and use a variety of advanced operations to move up to 232 bytes of data per transaction with minimal application or processor involvement.
Gen-Z supports point-to-point, daisy-chain, mesh, and switch-based topologies.
Gen-Z delivers maximum performance without sacrificing flexibility. This enables solution scalability and flexibility in choice of:
- Interconnect topology and routing algorithms.
- Switch design and implementation. Gen-Z supports a wide range of switch radix, buffer capacities, virtual channels, etc. from small to rack-scale solutions.
Gen-Z components and existing solution stacks can be transparently supported by unmodified operating systems and application middleware. Please review our educational materials and white papers for details.
Gen-Z specifies a physical layer abstraction that enables it to support multiple physical layers without impacting the higher-level functional blocks, enabling faster deployment of new physical layers and signaling rates. It also enables co-packaged solutions, discrete electrical solutions, and discrete optical solutions.
Yes, this enables processors, accelerators and I/O components that currently support PCI Express to quickly and readily integrate Gen-Z functionality. Signaling rates from 2.5 GT/s to 32 GT/s can be supported. Learn more here.
Gen-Z builds upon the IEEE 802.3 electrical layer specification. signaling rates from 25 GT/s to 112 GT/s PAM 4 can be supported.
To reduce power consumption, complexity, and cost, Gen-Z optimizes the 802.3 electrical layer to support different loss budgets and topologies, e.g., multiple loss budgets for chip-to-chip within an enclosure and fabric-distance loss budgets to connect multiple enclosures. In low-loss solutions, up to 80% power and cost reductions can be achieved.
Gen-Z architecture supports from 1 to 256 lanes per link. The number of provisioned lanes will vary based on solution requirements and the choice to avoid complex skew compensation technologies.
Gen-Z supports symmetric links where the number of transmit and receive lanes are equal. Asymmetric links provide numerous advantages. Review our educational materials for details.
Gen-Z can be used in discrete and co-packaged solutions.
Gen-Z architecture supports up to 4,096 components per subnet and up to 64k subnets. Initial products will be focused on simple, enclosure and rack-scale solutions.
Gen-Z is designed to work with a wide range of existing, high-volume mechanical form factors and cables including u.2, PCIe CEM, etc. Gen-Z will work with the new DDIMM (Differential DIMM) mechanical form factor for high-speed memory.
Yes, the Gen-Z Scalable Connector Specification supports multiple component types and use cases, including: memory (DRAM / NVM), FPGAs, GPUs/GPGPUs, DSPs, I/Os, NICs, SSDs, etc. With sufficient volume, current estimates indicate connector cost should be similar to existing low-cost, high-volume connectors. The Scalable Connector Specification v1.2 was developed by the Gen-Z Consortium and contributed to SNIA SFF as SFF-TA-1020. It can be viewed and downloaded here.
One of the primary goals of the Gen-Z Consortium is to create an open ecosystem and standards body where all companies can come together to quickly develop new technology.
From its inception, the Gen-Z Consortium wanted to maximize adoption of the Gen-Z Scalable Connector across market segments and use cases. The Gen-Z Consortium published the draft 0.9 specification to the industry in the hopes that multiple industry standards bodies and organizations would reference this connector, thus ensuring that all would benefit. However, due to concerns raised by some companies that are not members of the Gen-Z Consortium, the Board of Directors concluded that in the best interests of the industry, it would support submission of portions of the draft 0.9 specification to the SNIA SFF organization as a new SFF connector specification, and reference this new SFF connector specification in all applicable Gen-Z Consortium specifications.
Gen-Z Consortium members have determined that a mechanical form factor is required to address evolving solution needs. The attributes are:
- The mechanical form factor is modular to enable solutions to scale in the x, y, and z axis. This will increase solution flexibility and agility while ensuring interoperability across multiple use cases.
- The mechanical form factor can support multiple Gen-Z Scalable Connectors. Each connector provides incremental power, bandwidth and connectivity. For example, a mechanical form factor could support two 4C connectors that provide a total of 160W of power, 64 differential pairs, up to 8 links, etc. Support for multiple connectors simplifies solution development and eliminates mechanical complexity not possible when using alternative technologies.
- Gen-Z architecture enables solutions to scale to 1024 W. Similar to other technologies, a portion of the power will be delivered through the scalable connector(s) and remaining power will be delivered through separate high-capacity power cable attached to the power supply.
Gen-Z supports PCI and PCIe® technology in the following ways:
- Gen-Z supports the PCIe physical layer, enabling PCIe solutions to integrate Gen-Z with minimal disruption.
- Gen-Z supports PCI and PCIe configuration space, enabling an unmodified operating system to transparently use Gen-Z I/O components.
- Gen-Z components and switches may support PCIe Compatible Ordering (PCO), enabling an unmodified device driver to be transparently used with a Gen-Z I/O component. Though PCO solutions are constrained by the PCIe architecture, e.g., a single interface and a single path between an I/O component and a host system, they can still take advantage of a subset of the Gen-Z capabilities, e.g., low-latency switching. In contrast, non-PCO solutions can take full advantage of Gen-Z’s capabilities.
Yes, I/O components can take full advantage of Gen-Z capabilities:
- Low-latency switching
- Memory-speed (multiple GB/s) processor-to-device communications
- Security and fine-grain hardware-enforced isolation (any-to-any communication without compromise)
- Supports many more atomics than the three supported by PCIe
- Simplified single and multi-host I/O virtualization and sharing capabilities
- Multipath – transparent aggregation, resiliency, and robust topologies
- Very high-speed electrical and optical physical layers
- Gen-Z Scalable Connector and modular form factors
- CPU-based data movers to enable new software paradigms
- Scale-up and scale-out connectivity and performance, e.g., enables up to 8192 devices per SoC
- Simplified hot-plug management and scaling, e.g., eliminates OS rebalancing complexity that inhibits scalability
Yes, Gen-Z supports multiple processor architecture Atomics, including x86 / ARM / Power. More information here.
- Supports multiple data sizes – 8, 16, 32, 64, and 128-bit sizes
- Supports integer and floating-point data
- Supports arithmetic and logical operations
- Supports vector atomics, e.g., up to 32 32-bit data values
Gen-Z supports multiple collective operations including broadcast, barrier, scatter, gather, reduce, map reduce, etc. Further, these collective operations can be implemented in collective accelerators incorporated into a switch topology. Collective accelerators can improve performance, reduce the number of packets exchanged between components, and reduce the probability of congestion.
Yes, the Gen-Z Core specification describes multiple techniques to optimize load-to-use latency that can be incorporated into any design. The specification also describes techniques to enable media controller differentiation, solution-specific customizations, optimize power management, and more.
Gen-Z was created to simplify and unify data access at nearly any scale. At a very high level, Gen-Z provides functionality that supports more topologies, more scalability, and more use cases than what is in the market today.
- Gen-Z supports multiple topologies – co-packaged, point-to-point, mesh, switch-based, and transparent router topologies within a single enclosure or at rack scale.
- Gen-Z enables a robust, flexible, and extensible data access protocol that can access any type and number of components including: memory, I/O, accelerators, storage, FPGA, DSP, etc.
- Gen-Z supports two of the highest volume physical layers – the PCI Express® physical layer and an optimized version of the 802.3 electrical. More information here.
- Gen-Z uses a highly-optimized, memory semantic protocol that inherently supports multiple use cases, including memory (DRAM and Storage Class Memory (SCM)), I/O – Gen-Z native and logical PCI device support, block and hybrid SCM + block storage, coherent and hybrid accelerators, Ethernet-compatible networking, low-latency messaging, coherency, and more.
- Gen-Z supports up to 64-way memory interleaving across a set of point-to-point or switch attached memory components. More information here.
- Gen-Z supports hardware-enforced isolation and built-in security.
- Gen-Z supports nearly any routing algorithm.
- Gen-Z supports congestion management.
- Gen-Z abstracts memory media from the memory controller to enable the industry to deploy a wide range of memory media, which enables new media types or multiple generations of a given media type to be transparently supported in any solution.
- Gen-Z specifies a highly efficient and flexible protocol capable of supporting a wide range of application needs.
- Gen-Z simplifies hardware and software designs, reducing complexity, overheads, and end-to-end latency. Simple, efficient solution stacks ease deployment and security, speed innovation, and reduce development and support costs.
- Gen-Z supports a robust hardware-enforced isolation and security framework to help protect customer solutions from cyber threats. Components and resources can be isolated to prevent unauthorized access.
- Data plane and control plane communications can be fully authenticated to prevent tampering and anti-replay attacks. In addition, data payloads can be encrypted using industry or customer-driven algorithms and policies (encryption is performed within the source and destination components).
- Gen-Z interoperability enables the architecture to simultaneously and efficiently transport standard and customized communications between components, enabling customers and vendors to rapidly innovate and deploy new capabilities and services.
- Gen-Z breaks the processor-memory interlock and enables new types of memory media to be transparently deployed at an accelerated rate.
- Supports a wide variety of component types including processors, memory modules, FPGAs, GPUs / GPGPUs, DSPs, I/O, accelerators, NICs, custom ASICs, and more.
- Supports a wide range of physical layer signaling rates and types (electrical and optical), enabling hardware to optimize performance while minimizing package costs, to scale to any bandwidth and distance within an enclosure or across data center racks, and to provision multiple paths to provide aggregate performance and resilience.
- Processor agnostic. Solutions can be flexibly composed of any mix of processor types and capabilities. Gen-Z also specifies a common atomic protocol to ensure interoperability between any processor and any component type.
- Supports traditional processor-centric and new memory-centric solution architectures.
- Gen-Z can be inserted into existing processor-centric solution architectures..
- Supports new memory-centric architectures that minimize data movement, reduce power consumption, reduce latency, and increase data access parallelism, while taking advantage of Gen-Z multipath capabilities to increase aggregate performance and resilience, enabling new services.
Yes, the Gen-Z Consortium will periodically publicly post draft specifications and technical concepts to elicit input from the broader industry and directly from customers.
Member companies have created a variety of open source projects that are available to the broader industry. These are available on GitHub.
No, solutions will continue to incorporate existing interconnects where needed.
Please see member companies for their specific product plans. Multiple member companies have demonstrated solution concepts that highlight the benefits from using Gen-Z technology.
Each technology has been created to meet specific solution needs in terms of functionality, performance, scale, etc. The Gen-Z Consortium views these new technologies as complementary, open industry standards that will enable customer choice and drive innovation.
The Gen-Z Consortium™ is comprised of leading technology companies dedicated to creating and commercializing Gen-Z technology. The founding consortium’s members include: AMD, ARM, Broadcom, Cray, Dell EMC, Hewlett Packard Enterprise, Huawei, IDT, Micron, Samsung, SK hynix, and Xilinx. Refer to our Members List to see the full consortium membership.
The Gen-Z Consortium’s mission is to deliver a suite of specifications to enable Gen-Z to be integrated into any solution. The Gen-Z Consortium will establish an open ecosystem where customers and the industry can directly engage with one another in creating these specifications.
The Gen-Z Consortium was formed as a not-for-profit corporation. To join, a company executes a Membership Agreement. Twelve member companies hold Board of Director seats and provide overall governance. Board seats are voted on annually. All general member companies may participate in any Workgroup to develop the Gen-Z specifications and other materials. For more information on becoming a member of the Gen-Z Consortium please get in touch with our administrative team through our Contact Form.
The Gen-Z Consortium owns the copyrights and all of its final published specifications.
The Gen-Z Consortium made its public announcement on Tuesday October 11th, 2016.
A new industry body was created to enable customers and the industry to directly work together in an open ecosystem. This requires a new organizational structure and engagement model.
Refer to our Members Page for additional membership information.
No, the technical specifications are available via the consortium web-site free of charge. The Gen-Z Consortium does not charge an end user or implementer fee.
The Gen-Z Consortium™ and CXL™ Consortium Memo of Understanding (MoU) leverages the complementary aspects of both technologies. CXL™ and Gen-Z are low-latency, memory-semantic (read/write) protocols that enable the transition to memory-centric architectures. The MoU outlines the formation of common workgroups between both organizations to provide clear cooperation, defining bridging between the protocols while leveraging the strengths of both technologies. Read the press release for details.
The Memo of Understanding (MoU) agreement between The OpenFabrics Alliance (OFA) and Gen-Z Consortium advances the industry standardization of open-source fabric managementhat is adaptable to existing and emerging fabrics and is beneficial to the industry as it preserves client software investment as fabrics change and as new fabrics emerge. The MoU creates the framework for a series of technical exchange meetings between the two organizations to determine future activities. Read the media alert for more information.
The Gen-Z Consortium has an alliance with DMTF to develop extensions to the Redfish® API and other DMTF standards. The partnership also outlines collaboration with DMTF on extensions to DMTF’s Platform Management Components Intercommunication (PMCI) standards, including planned development of a new Management Component Transport Protocol (MCTP) Gen-Z Transport Binding Specification. In addition, both groups will create and maintain extensions to the Redfish® API to support Gen-Z management.
