Multiple industry-leading processors contain integrated memory controllers that support up to 8 DDR (double data rate) channels. Processors that support 8 DDR 3200 MT/s channels can deliver approximately 200 GB/s of application memory bandwidth. Future processors that support 8 DDR 6400 MT/s channels will deliver approximately 400 GB/s of application memory bandwidth.
The simplest way to integrate Gen-Z into a processor is to attach it to the processor-internal coherency logic, and allocate a portion of the processor’s address space to DDR and a portion to Gen-Z. When a processor core issues a load, store, or atomic request to memory, the request is routed to address comparison logic, which quickly determines whether to service the request through the DDR memory controller or through the Gen-Z logic.
Processors that augment their existing DDR designs with Gen-Z will deliver superior aggregate application memory bandwidth, as illustrated in the following table. If a processor repurposes its existing pins, such as those used for PCIe, then it can deliver superior bandwidth without adding new processor pins. Further, as processors move to support higher Gen-Z signaling rates, the aggregate application memory bandwidth will reach the multiple TB/s of application memory bandwidth that a growing number of applications and customers demand.