By Tim Symons, Storage Architect, Microchip
Gen-Z fabric incorporates a number of features for enabling low-latency, memory-semantic communication, and one of the key components of the Gen-Z ecosystem is the Gen-Z switch. The Consortium showcased a Gen-Z switch at Flash Memory Summit 2018 as part of our multi-vendor technology demonstration. The server rack display utilized Field-Programmable Gate Array (FPGA)-based Gen-Z bridges connecting compute nodes to memory pools through a Gen-Z switch.
The Gen-Z switch is the backbone of the Gen-Z fabric. It is essentially a component or component-integrated functionality that performs packet relay between component interfaces. The configuration of Gen-Z fabric is achieved and managed by a Fabric Manager that identifies all of the components attached to the fabric and executes policies for managing packets, creating domains, sub-domains, and access privileges by configuring the switches within the fabric. Fabric management is in-band using Gen-Z commands over Gen-Z connections.
To enable its full functionality, Gen-Z memory fabric involves switching, routing, security, zoning, access control and fabric management. The core properties of Gen-Z fabric consist of:
- Scalable and provisioned memory infrastructure
- Shared memory for data processing
- Connectivity of processors, GPUs, accelerators, and optimized engines
- Next generation DRAM, FLASH and storage class memory
- Enabling persistent memory
These characteristics are configurable to meet application needs by managing access to memory domains, high-speed routing zones, and processing domains. Fabric switches can interconnect to create a larger infrastructure and can also be provisioned into multiple subdomains and zones designed to support variable application workloads and system requirements.
Local switches enable small-scale Gen-Z fabrics, as well as routing and provisioning of resources with minimal switching latency and almost transparent routing. Peer-to-peer operation codes within the fabric ensure that direct attached memory is among the lowest latency Gen-Z fabric configurations.
Finally, it’s important to note that data integrity is paramount. Cyclic Redundancy Check (CRC) is performed at three levels: on the packet header, within a packet and optionally for each PHIT, to ensure error detection and to eliminate the possibility of a false packet acceptance.
At the higher link rates (53.125 Gb/s and above) Forward Error Correction (FEC) is implemented to correct PHIT bit errors that ensures data integrity and minimize retry events to optimize bandwidth utilization.
Gen-Z is truly the fabric for next-generation workloads. As the amount of data and multi-processing demands continue to increase, a high-bandwidth, low-latency interconnect is now imperative to meet the industry’s needs. Gen-Z technology delivers business and technology leaders a solution for overcoming current challenges within existing computer architecture and presents open, efficient, simple and cost-effective future solution opportunities.